(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating an improved buried strap in deep trench DRAM devices in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, a buried strap has been used in fabricating deep trench (DT)-based dynamic random access memory (DRAM) devices. The buried strap is a crucial part of the integration step connecting a storage node capacitor to an array switching transistor by forming a diffusion junction. Therefore, control of diffusion length and resistivity of the buried strap are key issues for a healthy interconnect between array devices and capacitors. The diffusion length varies with buried strap width which is subject to active area-deep trench overlay. To control the buried strap diffusion, thus controlling the junction connection between the transistor and the storage node, the buried strap width needs to be controlled regardless of active areaxe2x80x94deep trench misalignment. A fully self-aligned process along the active area width makes the device subject to a short between the active area and the deep trench feature along the active area width direction.
A number of patents have addressed aspects of DRAM fabrication. U.S. Pat. No. 6,211,006 to Tsai et al shows a trench-type capacitor. U.S. Pat. No. 6,124,206 to Flietner et al and U.S. Pat. No. 6,291,286 to Hsiao teach forming deep trench capacitors. U.S. Pat. No. 6,080,618 to Bergner et al discloses formation of a buried strap with little thickness variation. U.S. Pat. No. 6,037,194 to Bronner et al and U.S. Pat. No. 6,083,787 to Lee show deep trench DRAM""s and buried straps. U.S. Pat. No. 6,236,079 to Nitayama et al and U.S. Pat. No. 6,294,112 to Chakravarti et al show memory cells with deep trench capacitors. U.S. Pat. No. 5,985,768 to Speranza et al teaches a DRAM device. U.S. Pat. No. 6,008,104 to Schrems, U.S. Pat. No. 6,200,873 to Schrems et al, U.S. Pat. No. 6,140,175 to Kleinhenz et al, U.S. Pat. No. 6,130,145 to Ilg et al, U.S. Pat. No. 5,981,332 to Mandelman et al, U.S. Pat. No. 6,180,975 to Radens et al, and U.S. Pat. Nos. 6,204,112 and 5,909,044 both to Chakravarti et al all show BEST DRAM processes.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of BEST DRAM formation in the fabrication of integrated circuits.
It is a further object of the invention to provide a method of forming an improved buried strap in DRAM device fabrication.
A still further object of the invention is to provide a method of forming an improved buried strap in DRAM device fabrication where the active area is self-aligned to the deep trench only in the active area length direction.
Another object of the invention is to provide an improved buried strap formation method where the active area is self-aligned to the deep trench only in the active area length direction using a differential mask open scheme and a low selective silicon etch scheme with a thicker silicon nitride frame.
Yet another object of the invention is to provide an improved buried strap formation method using a selective hemispherical grain (HSG) and plasma doping method along with a differential etch with a silicon nitride frame.
A further object of the invention is to provide an improved buried strap formation method having a ground rule of less than or equal to 0.25 xcexcm in the fabrication of a DRAM integrated circuit device.
In accordance with the objects of the invention, an improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is achieved. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer. A capacitor and a buried strap are formed within the deep trench. A liner layer is deposited overlying the etch stop layer and the buried strap wherein the liner layer is of the same material as the etch stop layer. A hard mask material is deposited overlying the liner layer. The hard mask layer is etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches. The hard mask layer is removed and the isolation trenches are filled with a dielectric layer. The liner layer and the etch stop layer are removed. Gate electrodes are formed overlying the isolation trenches and the substrate. The substrate is annealed whereby dopants from the buried strap diffuse into the substrate to form a buried strap diffusion wherein the buried strap diffusion connects the deep trench capacitor to one of the gate electrodes to complete the buried strap deep trench DRAM device.
Also in accordance with the objects of the invention, an improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is achieved. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer. The etch stop layer is removed leaving behind a pad silicon nitride layer. A collar oxide is formed on top of the deep trench to isolate a storage capacitor with adjacent capacitors. A buried plate doping and a node dielectric layer formation are performed sequentially. The deep trench is filled with a silicon layer wherein the silicon layer forms an electrode of the deep trench capacitor. The silicon layer is recessed below a top surface of the substrate to leave a recess. A doped polysilicon layer is deposited into the recess to form a buried strap. A liner layer is deposited overlying the pad silicon nitride layer and the buried strap wherein the liner layer may be the same material as the pad nitride layer. A hard mask material is deposited overlying the liner layer. The hard mask layer is etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches. The hard mask layer is removed and the isolation trenches are filled with a dielectric layer. The liner layer and the etch stop layer are removed. Gate electrodes are formed overlying the isolation trenches and the substrate. The substrate is annealed whereby dopants from the buried strap diffuse into the substrate to form a buried strap diffusion wherein the buried strap diffusion connects the deep trench capacitor to one of the gate electrodes to complete the buried strap deep trench DRAM device.